Baseband communications systems involve the transmission of bits over an electrical or optical line. The transmitter sends the data bits in one of several formats, such as PAM (Pulse Amplitude Modulation) or NRZ (Non-Return to Zero) modulation. Modern systems carry data bits of multiple Giga-bit rates over electrical wire, back planes, board traces and/or over optical fibers. Examples are SAS and SATA disk data transfer protocols operating at 1.5 Gbps, 3.0 Gbps, 6 Gbps and 12 Gbps.
When the data bits are carried over the electrical or optical media, the signal is impaired by several effects. These include, among others: power supply noise; cross talk; frequency dependence of the channel transfer function; DC offset; and clock jitter, clock frequency, and phase offsets at the transmitter and receiver. It is the task of the receiver to recover the transmitted bits from the impaired received signal.
In receivers of SERDES systems, the high-speed line signal is sampled serially and the recovered bits are output in groups, in parallel, at a lower rate. For instance a SERDES for a 6 Gbps line rate might sample the line rate at 6 Gbps and output the recovered data to a 10-bit bus at 600 MHz or a 20-bit bus at 300 MHz.
In most analog SERDES receivers, the local bit recovery clock is carefully and precisely synchronized with the baud rate of the received signal. Then, at each receiver clock cycle, the signal is sampled at the center of the baud to recover the transmitted bit. Additional equalization may be applied to undo some of the channel distortion and to improve the BER (Bit Error Rate).
In most DSP (Digital Signal Processing) based asynchronous SERDES receivers, the local bit recovery clock is not synchronized, and instead the received analog signal is first sampled and digitized at the ADC (Analog to Digital Converter) using the DSP clock. A DSP interpolator is applied to recover the data bits, and its interpolation index is calculated by a DSP based TR (Timing Recovery) circuit. To this end the received signal is sampled at a rate higher than the baud rate. The over sampling rate may be 1.5×, 2×, 3× or even 4× depending on the desired interpolation and timing tracking performance at the given signal impairments. Typically the asynchronous DSP clock frequency may be several hundreds or even thousands of ppm (Parts per Million) offset from the transmit clock.
To perform the data recovery, the TR supplies a regularly updated interpolation index to the interpolator, which calculates the signal amplitude at that index. This calculated signal amplitude is then used to recover the transmitted data bit. Often this simply involves determining the sign of the interpolated signal at the desired interpolation index. In some systems an equalizer may be applied, which calculates an equalized amplitude from the interpolated amplitude. The equalizer may comprise a FFE (Feed Forward Equalizer) and/or a DFE (Decision Feedback Equalizer).
In many applications, the electrical distortion and other impairments of the received signal are not fixed and pre-determined but rather depend on use, application, deployment and other time varying factors such as temperature. To this end the equalizer will apply adapted coefficients.
When the final SERDES system is validated, it is assessed in terms of its tolerance to SJ (Sinusoidal jitter) under various operating conditions. This is a characterization based on the BER (Bit Error Rate) of the received signal. While the SJ characterization provides a measure for timing tracking in the presence of frequency offset and other timing jitter, it does not provide detailed insight into the causes of any low performance, whether in experimental or production systems.
When the SERDES system is implemented with an ASIC (Application Specific Integrated Circuit), in known approaches these measurements are performed at the input to the ASIC, as there is generally no ability to probe into the ASIC. As a result, the probed signal represents the impaired signal at the input to the ASIC. Any additional impairments originating within the ASIC are not represented. Moreover, any processing performed within the ASIC is also not represented.
Moreover, these measurements require costly measurement equipment that is not always readily available when poor performance requires deeper investigation of the received signal. These measurements are also cumbersome to set-up and difficult to use at a customer site or by the customer.
Improvements in the measurement of impairments of the received signal are desirable.